The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is the quintessential device of contemporary human civilization, powering every microprocessor and memory cell on Earth. By tuning an external gate voltage, surface electrostatics can invert the semiconductor majority carrier type, modulating an ultra-thin conductive channel with microscopic precision.
1. The MOS Capacitor and Surface Electrostatics
Consider an ideal MOS structure on a p-type Silicon substrate ((N_A)) with an insulating gate dielectric (e.g., ( ext{SiO}_2) or ( ext{HfO}_2)) of thickness (t_{ ext{ox}}) and permittivity (psilon_{ ext{ox}}). Let (psi(x)) denote the electrostatic potential as a function of depth (x) into the semiconductor ((x = 0) at the oxide-silicon interface, (psi(infty) = 0) in the bulk). The surface potential is (psi_s = psi(0)).
Depending on the gate voltage (V_G), three distinct electrostatic regimes arise:
- Accumulation ((psi_s < 0)): Holes accumulate at the interface, forming an ultra-dense positive surface charge sheet.
- Depletion ((0 < psi_s < phi_B)): Holes are repelled into the substrate, exposing negative ionized acceptors ((N_A^-)). The depletion width (W_d) grows with surface potential:
[
W_d = sqrt{rac{2psilon_s psi_s}{e N_A}}
] - Strong Inversion ((psi_s ge 2phi_B)): When (psi_s) exceeds twice the bulk Fermi potential (phi_B = rac{k_B T}{e} ln(N_A / n_i)), the conduction band edge (E_c) bends below the Fermi level (E_F) at the surface. The minority electron concentration at the surface exceeds the majority hole doping in the bulk ((n_s ge N_A)), establishing a conductive n-type inversion layer.
2. Threshold Voltage Derivation
The threshold voltage (V_{ ext{th}}) is defined as the gate voltage required to achieve strong inversion ((psi_s = 2phi_B)). Summing the voltage drops across the gate oxide and the semiconductor interface:
[
V_G = V_{ ext{FB}} + psi_s + rac{|Q_s(psi_s)|}{C_{ ext{ox}}}
]
where (V_{ ext{FB}} = Phi_{ms} – rac{Q_{ ext{ox}}}{C_{ ext{ox}}}) is the flat-band voltage, and (C_{ ext{ox}} = rac{psilon_{ ext{ox}}}{t_{ ext{ox}}}) is the gate oxide capacitance per unit area. At the onset of strong inversion, the depletion charge reaches its maximum value:
[
Q_{d,max} = -sqrt{2 e psilon_s N_A (2phi_B)}
]
Substituting into the potential balance equation yields the classic threshold voltage expression:
[
V_{ ext{th}} = V_{ ext{FB}} + 2phi_B + rac{sqrt{4 e psilon_s N_A phi_B}}{C_{ ext{ox}}}
]
3. Current-Voltage Characteristics: The Gradual Channel Approximation
In a planar n-channel MOSFET with channel length (L) and width (W), applying a drain-source bias (V_{ ext{DS}}) drives drift current through the inversion layer. Under the Gradual Channel Approximation (GCA) (assuming the vertical electric field from the gate dominates over the lateral field along the channel), the mobile inversion charge per unit area at position (y) along the channel is:
[
Q_i(y) = -C_{ ext{ox}} [V_{ ext{GS}} – V_{ ext{th}} – V(y)]
]
The drain current is purely diffusive/drift along the channel: (I_D = -W Q_i(y) v_d(y) = W mu_n C_{ ext{ox}} [V_{ ext{GS}} – V_{ ext{th}} – V(y)] rac{dV}{dy}). Integrating from source ((y = 0, V = 0)) to drain ((y = L, V = V_{ ext{DS}})) yields:
[
I_D = mu_n C_{ ext{ox}} rac{W}{L} left[ (V_{ ext{GS}} – V_{ ext{th}}) V_{ ext{DS}} – rac{1}{2} V_{ ext{DS}}^2
ight] quad ( ext{Linear Regime: } V_{ ext{DS}} < V_{ ext{GS}} – V_{ ext{th}})
]
When (V_{ ext{DS}}) reaches (V_{ ext{DS,sat}} = V_{ ext{GS}} – V_{ ext{th}}), the inversion charge at the drain edge pinches off ((Q_i(L) o 0)). Beyond pinch-off, the current saturates at a constant value governed by the quadratic law:
[
I_{D, ext{sat}} = rac{1}{2} mu_n C_{ ext{ox}} rac{W}{L} (V_{ ext{GS}} – V_{ ext{th}})^2 quad ( ext{Saturation Regime})
]
In ultra-short nanoscale channels ((L < 20 ext{ nm})), velocity saturation ((v o v_{ ext{sat}})) and quantum mechanical carrier confinement renormalize this quadratic relationship into a linear dependence on ((V_{ ext{GS}} – V_{ ext{th}})).
